In the field of this invention it is known that a fractional-N PLL implemented for GSM (Global System for Mobile telecommunications) standards employs a sigma-delta modulator such as the Multi Accumulators noise Shaping (MASH) II or MASH III architecture. These systems were first described in the IEEE paper: “A multiple modulator fractional divider”, May 1990 by B. Miller and B. Conley. Such systems provide a corrected quantization noise spectrum shape for a synthesised non-modulated frequency.
Modern radios use fractional-N PLLs to synthesize the carrier frequency of the radio, as shown in the circuit of FIG. 1. A reference signal is synthesized from a stable and known reference frequency 10. This is fed to a voltage controlled oscillator (VCO) 40 via a phase-frequency detector (PFD) 20 and a loop filter 30. The VCO 40 outputs a carrier signal according to its tuning voltage. Control of the tuning voltage is achieved by a feedback loop which provides a feedback signal to the PFD 20 via a multi modulus divider (MMD) 50, which in turn is controlled by a digital sigma-delta modulator 60 coupled to receive a digital number 70 indicating the frequency location of a carrier.
The PFD 20 compares the phases between the reference frequency 10 and the feedback signal, which is the output of the VCO 40 after being divided. Finally, the loop filter 30 (a low-pass filter) smoothes the output of the PFD 20 and provides it to the VCO 40. In locked conditions, both inputs to the PFD 20 have the same frequency and phase.
Therefore, the frequency synthesized is a multiple of the reference frequency 10, controlled by the digital sigma-delta modulator 60 that drives the MMD 50. The loop dynamic, principally defined by the loop filter 30, has the ability to average the division ratio. Therefore if the MMD 50 is modulated fast enough by the digital sigma-delta modulator 60, the frequency synthesized is a fractional multiple of the reference frequency 10.
There are a wide range of techniques that modulate the MMD 50 to provide the desired average division ratio. The main drawback of these known techniques is the quantization noise injected into the loop. Much effort has been expended to provide arrangements which reduce the amount of noise added and several solutions have been proposed using sigma-delta modulators which attempt to overcome this major problem.
Such arrangements perform noise shaping in the form of a high pass characteristic that is removed from the low-pass loop filter 30. The MASH III structure is popularly used due to its ability to generate shaped quantization noise.
A problem with this known arrangement is that removing the quantization noise implies constraints on the loop filter bandwidth that reduce the loop lock time and enlarges the modulation phase error when performed through the modulator.
Furthermore, implemented in a frequency synthesizer for GSM standards, this limitation degrades the direct modulation phase error and reduces the PLL lock time. A further known arrangement, the MASH IV structure, can mathematically reach the desired performance criteria, but provides an output range twice that of the MASH III structure. Therefore, the loop non-linearity is exercised twice and degrades performance by increasing the overall phase noise.
A need therefore exists for a fractional-n PLL frequency synthesizer wherein the abovementioned disadvantage(s) may be alleviated.